📅 Jul 31
Architect and deliver a kernel-authoring SDK and lowering tools for a novel dataflow architecture, shaping APIs and software practices while solving end-to-end hardware and software challenges.
D-Matrix jobs
d-Matrix builds memory-centric computing technology for efficient, low-latency AI inference.
🏢 Technology🤖 AI Computing Hardware And Infrastructure
34 open roles at D-Matrix
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📅 Jul 28
Develop and optimize software kernels for machine-learning operators on next-generation AI hardware, while improving SDK usability and performance analysis across the software toolchain.
📅 Jul 28
Productize and maintain next-generation AI inference deployment software, building scalable system infrastructure and optimizing the full software toolchain in collaboration with machine learning, compiler, and hardware teams.
📅 Jul 15
Develop and optimize software kernels for next-generation AI hardware, mapping machine-learning workloads and computational graphs to specialized architectures while collaborating across compiler, software, and hardware teams.
📅 Jul 15
Develop and optimize software kernels for next-generation AI hardware, mapping machine-learning workloads to specialized architectures and collaborating across compiler, software, and hardware teams.
📅 Jul 15
Develop and evaluate algorithms that improve large language model inference performance on DNN accelerators, balancing latency, throughput, memory efficiency, numerical precision, and model quality.
📅 May 6
Define and lead hardware qualification strategies for AI compute platforms, validating reliability from ASIC packages to rack-scale systems and driving fixes that bridge design and production.
📅 Mar 11
Analyze emerging machine-learning workloads and develop performance models and hardware-software features for current and future AI inference accelerators, collaborating across architecture, hardware, compiler, server, and kernel teams.
📅 May 20, 2025
Lead analog-mixed-signal IC design for AI inference accelerators, owning in-memory-compute and die-to-die interface circuits from schematic through silicon bring-up while meeting low-power targets.
📅 Apr 3, 2025
Lead SoC and IP design verification from architecture through tape-out and silicon bring-up, building UVM-based environments and driving debug, coverage closure, and verification sign-off.
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