Lead thermal-fluid design, architecture, and validation for AI computing platforms, developing air- and liquid-cooled solutions from XPU cold plates through high-power racks and qualifying them through simulation and testing.
D-Matrix jobs
d-Matrix builds memory-centric computing technology for efficient, low-latency AI inference.
34 open roles at D-Matrix
Director, Quality and Reliability Engineering โ AI Hardware
Leads quality and reliability strategy for AI hardware platforms, owning product, supplier, manufacturing, and customer quality while building a team and ensuring dependable data-center-scale deployments.
Build and lead investor relations from the ground up, shaping the companyโs equity story, investor communications, financing support, and public-market readiness in partnership with executive leadership.
Leads global talent acquisition strategy and execution, builds the employer brand, closes critical technical and leadership hires, and develops recruiting teams, operations, and candidate experience.
Own end-to-end performance of inference workloads across orchestration and serving stacks, using profiling and evidence-driven fixes to protect throughput, latency, and stability at scale.
Own end-to-end testing and release engineering for Inference Cloud, building automated tests across shared GPU and accelerator hardware and enabling reliable, independently released components.
Define and build production AI-enabled automation across build, CI, testing, and release, setting technical direction and delivering tools that improve engineering workflows while preserving correctness.
Own first response and end-to-end resolution across Kubernetes, CI/CD, Linux systems, and demo environments, while improving reliability through automation, monitoring, alerting, and runbooks.
Leads software quality strategy and test engineering across firmware, compilers, runtimes, and inference serving, building automation and AI-assisted practices while improving release confidence and team capability.
Lead d-Matrixโs Bazel build-out by completing the migration and building production remote execution, hermetic toolchains, and reliable caching to reduce build and CI times across engineering teams.
Own strategic enterprise accounts and lead technically complex sales cycles for AI inference hardware and software, from initial evaluation through production deployment, while building scalable sales processes and forecasts.
Lead strategic sales for AI infrastructure products, owning complex enterprise sales cycles from technical evaluation through production deployment while building account growth, forecasting, and scalable sales processes.
Build reliable automation that diagnoses CI/CD failures, identifies breaking merges, and improves release engineering across cloud and on-prem build and test systems.
Build and lead a unified information security function, protecting semiconductor design IP, software supply chains, AI systems, and corporate, cloud, and lab infrastructure while enabling secure development and product delivery.
Own reliability, automation, and observability across colocation, on-premises, cloud, and customer-facing infrastructure, from bare-metal provisioning through Kubernetes operations and incident response.
Build and lead the SRE function, owning reliability across data centers, lab clusters, cloud environments, and platform services while setting technical direction, developing the team, and improving operational resilience and efficiency.
Architect and develop runtime software, low-level drivers, and systems software for AI inference silicon, owning runtime performance and making architectural decisions that help chips run reliably in production.
Own pre-silicon power estimation for AI accelerators, build workload-based architectural power tools, and drive power-performance improvements across microarchitecture, RTL, physical design, and silicon validation.
Leads high-complexity PCB layout for AI accelerator cards and system boards, owning high-speed signal integrity, power delivery, design methodology, automation, and manufacturing readiness.
Own transistor-level design of high-speed SerDes transmit and receive datapaths, from architecture and verification through layout, silicon bring-up, and bench characterization.
Own transistor-level design of high-speed SerDes clocking blocks, from PLL, phase interpolator, and CDR architecture through verification, layout, silicon bring-up, and characterization.
Build and optimize end-to-end LLM inference systems, from custom kernels and distributed runtimes to serving APIs, while prototyping heterogeneous deployments and shaping how frontier models use next-generation hardware.
Own full-cycle recruiting for engineering and technical roles, partnering with hiring managers to define hiring needs, build talent pipelines, and deliver a strong candidate experience.
Lead end-to-end post-silicon and systems hardware programs, coordinating global engineering teams, establishing predictable milestones, and improving delivery planning, execution, and cross-functional collaboration.
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