Aurelius is the autonomous directed energy company.
We are a group of engineers, operators, and company patriots building American-made, laser-based counter-UAS systems that neutralize aerial threats.
Archimedes, our autonomous laser turret, combines a high-power laser with radar and machine vision to find, track, and defeat small drones. We design in San Francisco, manufacture in Detroit, and test onsite, on our own cUAS range.
You'll own hardware architecture across Archimedes and take subsystems from working prototype to hardware that ships and survives in the field.
You've done the full cycle more than once, you know where systems break and where teams get stuck, and you still like doing the hardest part yourself. As a Principal Hardware Engineer you will set the system-level hardware architecture, close the hardest design and manufacturing trades, and stand up the release path with Manufacturing. You'll work daily with electrical, power, embedded, optics, and manufacturing, and stay close enough to the bench and the floor to catch what the model misses.
Track record taking complex hardware the full cycle from prototype through manufacturing and field deployment, more than once
Deep mechanical expertise plus real judgment in at least one of electrical, power electronics, or embedded
Comfort being the technical anchor on a small team, still hands-on, not the manager of a large org
Evidence of systems that had to survive real-world shock, vibration, and environmental conditions
U.S. citizenship (required for export control).
Priority deliverables in the first 6 months:
A system-level hardware architecture and integration plan across mechanical, electrical, power, embedded, and optics
The hardest open design trades closed, with documented decisions on cost, mass, reliability, and field performance
A hardware release and production process with the Detroit manufacturing hub
Design review and documentation standards the rest of the hardware team can run against
Hands-on debug and characterization of the current system so field failures get fixed at the root, not patched
It would help if…
Directed energy, laser, or high-power systems experience
Defense or aerospace program experience with MIL-STD or equivalent environmental qualification
You've stood up a production line, or worked tightly with the manufacturers who did
Active security clearance or ability to obtain one.
You're a people manager without recent hands-on hardware work
Your experience is simulation only, limited to one narrow subcomponent, or purely consumer products
You need remote or hybrid work
At Aurelius we work what we call, 5+X. Our core operating hours are 5 days a week, Monday to Friday, 9am to 6pm Pacific Time.
The X is the honest acknowledgment that hard work sometimes takes more. That can be late nights and weekends during sprints and ramp-up periods or conferences, deployments, and events when the mission calls for it.
This role is onsite 5 days a week in San Francisco.
At Aurelius Systems, we invest in our people. Our comprehensive, competitive benefits package is available at little to no cost to employees and supports health, recovery, and whatever comes next. Explore Our Benefits.
This role requires access to export-controlled information or items and requires U.S. citizenship.
Email our Head of Talent, alfredo@aureliussystems.us with your resume, GitHub, or a link to the most extraordinary thing you've built or done.
Lead the design and production readiness of GPU servers and rack-scale infrastructure, translating vendor architectures into reliable, serviceable systems optimized for AI and high-performance computing workloads.
Lead silicon IP and subsystem architecture, microarchitecture, and implementation for AI hardware, translating functional and security requirements into designs and driving integration, validation, and cross-functional execution.
Lead hardware systems development for photonic AI infrastructure, taking board and system solutions from concept through production while guiding integration, validation, and cross-functional engineering.
Lead RTL design from microarchitecture through tapeout for novel computing hardware, shaping architecture, guiding the RTL team, and partnering across verification and physical design to achieve design closure.
Own SoC subsystem development and third-party IP integration, help define processor architecture, and drive low-power design, PPA optimization, and timing closure through customer-ready releases.
