Own the mechanical design and integration of AI inference hardware from accelerator to rack, defining thermal performance, serviceability, manufacturing readiness, and reliability through qualification and production.
Normalcomputing jobs
Applied AI company developing new AI hardware and silicon solutions.
33 open roles at Normalcomputing
Extend the compiler frontend and intermediate representation to bring up emerging LLM architectures, preserve their quantization and numerical behavior, and validate models on simulators and FPGA prototypes.
Lead development of a hardware simulator and compiler-integrated debugging and profiling tools, balancing fidelity, performance, and usability so compiler and runtime teams can validate evolving hardware before silicon.
Develop firmware for an embedded processor on an SoC, bridging higher-level software to AI acceleration hardware while collaborating across hardware and software teams and verifying production-quality performance.
Develop algorithms and numerical methods for efficient LLM inference on in-memory hardware, co-designing with hardware teams and validating performance through simulation, FPGA prototypes, and silicon.
Lead cross-functional technical programs across silicon, systems, manufacturing, and software, translating company objectives into milestones and keeping engineering delivery on schedule.
Own DFT architecture and implementation for next-generation ASICs, driving scan, ATPG, MBIST, integration, verification, and manufacturing test readiness from RTL through tapeout and silicon bring-up.
Leads silicon product engineering from tape-out through high-volume manufacturing, owning packaging, test, validation, yield, qualification, and production calibration while building the team and partner ecosystem.
Build and calibrate transaction-level models of physics-inspired ASICs, correlating results with RTL, FPGA prototypes, and synthesis to guide performance predictions, verification, and hardware architecture decisions.
Architect processing-in-memory hardware from memory architecture and circuit design through modeling, manufacturer engagement, tapeout, and validation to improve AI inference performance.
Design and develop mixed-signal circuits, library cells, and macros for an unconventional computing architecture, owning analog development from exploratory design through silicon bring-up.
Leads end-to-end architecture for AI compute hardware, translating workload needs into system designs across boards, chassis, and racks, and guiding integration, validation, and deployment.
Leads RTL design for thermodynamic hardware from microarchitecture through tapeout, shaping architecture, guiding the RTL team, and partnering across verification and physical design to achieve signoff.
Leads the physical design team and end-to-end silicon implementation, from early floorplanning through timing and physical signoff to GDSII tapeout, while driving PPA and cross-functional feasibility.
Provides dedicated, discreet support to senior executives by managing complex calendars, travel, expenses, and communications while anticipating needs and coordinating seamless coverage across time zones.
Own foundry and manufacturing supplier relationships, negotiate capacity and long-term supply agreements, and build sourcing strategies and cost models that support custom silicon from prototype through scaled production.
The Media & PR Lead owns media relationships and public-relations programs, translating complex AI and silicon systems into compelling stories and leading announcements, speaking opportunities, and partner communications.
Own the architecture and implementation of a runtime that loads, schedules, and executes compiled programs on evolving AI hardware, while defining stable interfaces and optimizing LLM inference performance.
Design and build a custom compiler backend for LLM inference on novel hardware, owning code generation, scheduling, memory planning, fusion, and performance validation across simulators and FPGA prototypes.
Own full-cycle recruiting for senior hardware and silicon roles, partnering with engineering leaders to source specialized talent, calibrate technical requirements, and close candidates in a competitive market.
Own full-cycle recruiting for AI/ML, silicon, software, and G&A roles, partnering with hiring managers to source specialized talent, calibrate searches, and close candidates in a competitive market.
Coordinate the full recruiting process by scheduling interviews across time zones, maintaining Ashby and hiring reports, managing job postings, and supporting candidates, recruiters, and talent leadership.
Own the end-to-end physical design flow for complex silicon, from floorplanning and implementation through timing and physical signoff, tapeout, and post-silicon support.
Define silicon and system microarchitecture for custom AI accelerators, translating generative AI workloads into compute tiles, memory hierarchies, and interconnects while guiding co-design, modeling, and validation.
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