FPGA Implementation Engineer (JR)

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license.  Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role. Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.

Responsibilities:

Help deliver FPGA Platforms to internal groups to enable software development, and hardware-software pre-silicon validation.

Porting ASIC-specific code and models into FPGA-friendly models.

Define and run functional tests to prove the FPGA builds prior to FPGA distribution.

Perform FPGA synthesis, Implementation and Static Timing Analysis for complex ASIC designs.

Develop and maintain smoke tests to guarantee the quality of the deliverables from revision to revision.

Test the digital chip RTL from a user perspective on FPGA platforms.

Design and implement equivalent analog models to model the final ASIC analog front end.

Introduce model-based designing methods with the help of Simulink or Matlab framework and representation.

Required Skills and Qualifications:

Master's degree in Electrical Engineering, Computer Science, or similar field and 3+ years of directly related experience.

Experience using FPGAs and an understanding of how FPGA design differs from ASIC design.

Proficient in operating the simulation and modeling equipment including the design tools.

Knowledge of Verilog, System Verilog, and digital design concepts.

Verification/validation techniques and methodologies, including strong debugging skills.

Familiar with common on-chip bus protocols such as AMBA (AXI, AHB, APB) and communication protocols such as SPI, I2C, I2S, and UART.

Experience with Scripting for Hardware development (Python/Tcl)

Preferred Skills and Qualifications:

Experience in FPGA flows - Synthesis, Place & Route, and Timing closure, with emphasis on Synopsys Synplify and Xilinx Vivado.

Understanding of common FPGA primitives such as memories, I/O pads, BUFG, and MMCMs.

Experience with Object-oriented programming (OOP) in Python.

Experience with Floorplanning and advanced timing closure techniques.

Familiar with lab equipment such as Oscilloscope, Signal Generators and Logic Analyzers.

Solid documentation, communication, and interpersonal skills.

Work to tight and variable time scales.