📅 Aug 28
Own end-to-end PCB layout for high-speed, high-power AI compute hardware, from floorplanning and stack-up design through fabrication release, while supporting signal integrity, power integrity, and board bring-up.
Matx jobs
Chip maker serving the large model needs of frontier labs.
40 open roles at Matx
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📅 Aug 28
Leads mechanical design, thermal architecture, and system integration for rack-scale AI compute hardware, guiding trays, rack systems, liquid cooling, and manufacturing qualification from concept through production.
📅 Aug 28
Design and validate rack-scale mechanical systems for AI compute, including trays, enclosures, and liquid cooling hardware, while supporting integration, prototype builds, and manufacturing readiness.
📅 Jul 22
Own power estimation and optimization for AI accelerator SoCs, building energy models, analyzing workloads and implementation trade-offs, and partnering across architecture, RTL, and physical design.
📅 Jul 15
Own silicon verification from architecture and design specifications through tapeout, developing scalable testbenches and validation methods to deliver functionally accurate, high-performance compute silicon.
📅 Jun 15
Design and deliver silicon micro-architecture for compute, memory, and connectivity subsystems, driving work from architecture specifications through sign-off while partnering with verification, DFT, and physical design teams.
📅 May 27
Build and own the host-side runtime for custom AI accelerators, spanning device interfaces, compiler and kernel contracts, Python bindings, LLM inference serving, cluster recovery, and profiling.
📅 May 19
Design and deliver high-performance silicon from micro-architecture through sign-off, owning subsystem or chip-level work and driving design reviews, closure, and tapeout in collaboration with verification, DFT, and physical design teams.
📅 May 19
Prove correctness across hardware and compiler layers by verifying RTL, formalizing compiler transformations, and developing theorem-prover models that support functional and microarchitectural guarantees.
📅 Apr 13
Perform differential testing between RTL and a Rust cycle-accurate simulator, generate and minimize test cases, verify behavior against specifications, and improve simulation performance.
📅 Jan 27
Define, design, and validate rack-scale AI data center power architecture from rack to chip, developing efficient power delivery and voltage regulator solutions and guiding lab validation and system integration.
📅 Dec 19, 2024
Implement and verify DFT functions for advanced silicon, developing SERDES PHY test solutions, integrating PHY interfaces, and supporting silicon test programs from simulation through ATE.
📅 May 9, 2024
Own full-chip or subsystem silicon architecture for high-performance AI hardware, translating customer workloads and ML systems research into specifications and performance, area, and power trade-offs.
📅 Mar 12, 2024
Own and improve the ASIC physical design CAD flow from RTL to GDSII, automating back-end runs and deploying EDA tools and infrastructure to deliver performant, functionally correct silicon.
📅 Feb 16, 2024
Own ASIC and SoC physical design from RTL through production silicon, driving construction, sign-off, and cross-functional optimization to deliver high-performance, power-efficient designs through tapeout.
📅 Feb 16, 2024
Own SoC verification across subsystems and chip-level designs, building testbenches and driving coverage closure, verification reviews, and sign-off milestones from design specifications through tapeout.
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