🕒 2 days ago
Manage and improve analog and digital EDA environments, developing automated chip-design flows, supporting engineers and vendors, and enabling reliable use of tools and PDKs across advanced technology nodes.
Kandou-AI jobs
Develops Copper MIMO technology for AI systems and connectivity.
🏢 Technology🤖 AI Hardware And Connectivity
26 open roles at Kandou-AI
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🕒 2 days ago
Lead analog layout work for high-speed chip-to-chip communication and memory I/O, owning circuit layout and verification, supporting IP and chip integration, and collaborating with design teams and customers.
🕒 3 days ago
Own end-to-end delivery of DSP-based active cable programs from proposal through production, coordinating global engineering teams and Taiwan-based suppliers to meet technical, cost, quality, and schedule commitments.
📍 🇹🇼 Taipei - Hybrid💼 Full-Time🎙️ Leadership📮 Program Manager📢 🇬🇧 English Required📢 🇨🇳 Mandarin Required
Customer Platform, SDK & Interoperability Architect - Randa 1.6T AEC Platform
🕒 19 days ago
Kandou-AI🏢 Technology🤝 B2B
🕒 19 days ago
Architect the customer-facing software platform, SDK, APIs, and interoperability strategy for Randa, enabling reusable customer integrations and secure, backward-compatible releases across high-speed hardware platforms.
🕒 19 days ago
Leads platform validation for Ethernet retimers, owning pre- and post-silicon test strategy, bring-up, automation, system debug, and release readiness while guiding the Hyderabad validation team.
🕒 19 days ago
Leads hands-on delivery of embedded firmware modules for ASIC products, from design and coding through bring-up, validation, and release, while coordinating work and mentoring engineers.
🕒 19 days ago
Own end-to-end performance characterization of retimer silicon and active electrical cable channels, deriving defensible datasheet limits and guard-bands for validation, manufacturing, and customer specifications.
🕒 19 days ago
Lead hands-on development and delivery of real-time embedded firmware for a high-speed active electrical cable platform, owning implementation quality, silicon bring-up, testing, and mentoring.
📅 Sep 24
Architect high-speed interconnect software for AI memory systems, owning the CMIS stack, hyperscaler interoperability, manufacturing test orchestration, telemetry, and customer SDKs while ensuring standards compliance.
📅 Sep 18
Own block-to-chip physical implementation of high-speed communication IP, driving synthesis, placement, clocking, routing, timing closure, and physical sign-off to meet power, performance, and area targets in advanced FinFET nodes.
📅 Sep 8
Design control circuitry for very high-speed serial links and contribute to high-performance digital VLSI systems and architectures as part of an Advanced R&D team.
📅 Sep 7
Maintain lab computers, FPGA boards, silicon validation setups, and test equipment while supporting hardware setup, circuit debugging, inventory control, and safe lab operations.
📅 Aug 19
Develop and maintain digital verification methodologies and environments for complex FPGA or ASIC designs, partnering with designers to plan tests, close coverage, debug issues, and deliver projects on schedule.
📅 Aug 19
Partner with the CTO to research, model, and prototype communication and interconnect architectures, translating advances in signaling and system design into silicon-ready concepts for next-generation AI hardware.
📅 Aug 19
Lead end-to-end bring-up and validation of complex SoC platforms, setting test strategy and sign-off criteria while guiding engineers and coordinating across design, firmware, architecture, and system teams.
📅 Aug 19
Own physical design implementation from RTL to GDS, driving timing closure, signoff, verification, and chip-level integration while partnering with architecture, RTL, and DFT teams to deliver production-ready silicon.
📅 Aug 19
Validate high-speed integrated circuits and communication protocols, debug PCBs and ICs, develop test scripts, and support customers, field teams, and product design and certification activities.
📅 Aug 19
Develop and maintain bare-metal firmware for silicon products, build software tests, migrate silicon debug tools, and support design infrastructure while debugging real-time embedded systems.
📅 Aug 19
Define and lead firmware architecture for high-speed SerDes retimers, owning link training, adaptation, FEC, telemetry, standards compliance, and silicon bring-up from first samples through production.
📅 Aug 19
Design and verify high-performance digital circuits for next-generation communication and memory interfaces, from architecture and RTL through synthesis, silicon validation, debugging, and productization.
📅 Aug 19
Design and verify high-speed digital circuits for serial data links and memory interfaces, translating system requirements into block specifications and supporting chip integration, lab bring-up, and productization.
📅 Aug 19
Implement and debug DFT solutions for complex semiconductor designs, developing test patterns and timing constraints while collaborating with test and production teams to bring up devices.
📅 Aug 19
Characterize high-speed SerDes silicon across PVT, lead electrical measurements and test automation, and collaborate with design teams to evaluate transmitter and receiver performance.
📅 Aug 19
Develop system-level models for serial communication links, budget link performance, define transceiver block specifications, and collaborate with analog, digital, and verification teams throughout design and verification.
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