MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability.
The compute subsystem implements all of the core numerics and the associated control and data paths required to realize meaningful hardware acceleration of our target ML workloads. In this role you own the micro-architecture and RTL for blocks within it, end to end.
Contribute to MatX's silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, and fullchip design
Own entire subsystems or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off-ready design
Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, and area and timing closure toward various silicon milestones including design freeze and tapeout
Work closely with the verification, DFT, and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results
At least 5 years of silicon design experience
Tape-out experience — you have taped out chips, demonstrating end-to-end ownership of a design through multiple generations
Ability and willingness to ramp on Bluespec — a functionally-rooted HDL used for our designs. Prior Bluespec, or familiarity with functional-programming paradigms (e.g. Haskell), is a plus
Production-proven experience with silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management, and related functionalities
Experience with SystemVerilog, Python, C/C++, and similar scripting and programming languages for chip design and related flows
Experience testing your designs and working closely with verification teams toward performance and coverage closure goals
Hands-on experience with design synthesis, design lint, and related flows to take designs to high-quality sign-off
Experience designing arithmetic/compute datapaths for ML — matmul / systolic (MAC) arrays, reduction trees, and floating-point / special-function units (e.g. MuFu)
Familiarity with verification, emulation platforms, and methodologies
A lot of experience with logic that focuses on moving, storing, or managing data such as caches, buffers, crossbars, etc.
The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job-related skills, and relevant education and training. Career length is only a guideline for compensation.
Mid Career — $175,000 – $400,000 + equity
Senior Career — $250,000 – $600,000 + equity
What We Offer
Time off: 4 weeks PTO (accrued) + 12 company Holidays + up to 3 weeks remote work
Health: Company-subsidized Medical (Kaiser or Anthem) for employees & dependents, Guardian Dental and Vision insurances for employee & dependents, and life insurance (employee only), plus HSA and FSA offerings via Lively.
Financial Security: Choose from Roth or pre-tax 401K (or both) with a 5% company contribution (even if you don't contribute), 100% company-paid life insurance (up to $300K), long-term disability and travel insurance.
Professional Development: $1500 per year Professional Development Budget
Team Meals: MatX provides onsite team lunch & dinner Monday - Friday, with your choice of ordering via WeBox, Specialty’s or via our reimbursement system
Commute on Us: We pay 100% for your daily commute. Commute via our company rideshare account, reimburse public transportation, or get a Fasttrak card (or all three)
MatX E[x]tras: $50/mo to use on the perk you value most
Cell & Internet Reimbursement: $35/mo for cellular and $40/mo for wifi
Remote Home Setup: Use our Amazon business account for up to $1000 in office setup purchases.
Mental Wellbeing: 100% paid mental health benefit via SpringHealth and Guardian EAP.
Support to Parents: Up to 12 weeks paid parental leave regardless of path to parenthood, 10 weeks pregnancy disability leave, flexible return-to-work hours, and a $6K Family Fund to cover fertility, surrogacy, adoption, menopausal health, preservation, family counseling and more.
As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances.
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This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicant's capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.
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MatX does not accept unsolicited resumes from individual recruiters or third-party recruiting agencies in response to job postings. No fee will be paid to third parties who submit unsolicited candidates directly to our hiring managers or People team and any resumes submitted are deemed to be the property of MatX.
Desenvolve lógica FPGA para criptografia e redes de alto desempenho, desde processamento de pacotes e integração de núcleos criptográficos até verificação, processamento de sinais e suporte à certificação.
Own verification of compute hardware from block and subsystem testing through full-chip validation, software qualification, coverage closure, and sign-off milestones leading to design freeze and tapeout.
Lead RTL design and integration for next-generation wafer-scale AI processors, driving high-performance, power-efficient chip architecture from specification and microarchitecture through silicon bring-up.
Design and verify digital CMOS circuits and architectures for advanced mixed-signal SoCs, contributing from concept through production while collaborating across engineering teams and supervising junior engineers.
Design and verify high-speed digital circuits for serial data links and memory interfaces, translating system requirements into block specifications and supporting chip integration, lab bring-up, and productization.
