Senior DFT Engineer

We have an exciting opportunity for a talented DFT Engineer to join our growing team in Edinburgh. In this role, you will play a key role in defining and implementing robust DFT architectures across complex digital designs, enabling high manufacturing test coverage, silicon bring-up, and product reliability.

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license.  Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role. At Cirrus Logic, we believe that diversity drives innovation, and we are committed to encouraging an open and collaborative culture where different approaches, ideas, and points of view are respected and valued. We aim to promote a workplace where everyone can contribute irrespective of race, colour, national origin, religion or belief, gender or gender identity, sexual orientation, age, marital status, pregnancy status, or disability.

Responsibilities:

Define and implement chip-level and block-level DFT strategies for complex ASICs

Develop and integrate scan architecture, compression logic, boundary scan, MBIST, and LBIST solutions

Drive ATPG generation, fault simulation, diagnosis, and coverage closure

Collaborate with RTL, verification, physical design, and test engineering teams

Support synthesis, STA, and physical design flows with DFT based constraints

Perform DFT verification using simulation

Lead silicon bring-up, debug and failure diagnosis activities

Develop automation scripts and methodologies to improve DFT productivity and quality

Required Skills and Qualifications:

Bachelor's, Master’s or PhD degree in Electrical Engineering or related discipline and proven industry experience in a DFT position

Strong understanding of digital design and test methodologies

Hands-on experience with:

Scan insertion and scan compression

ATPG and fault simulation

MBIST/LBIST implementation

JTAG / IEEE 1149.1 standards

Test coverage analysis and diagnosis.

Experience with industry-standard EDA tools such as:

Siemens Tessent

Synopsys TetraMAX / TestMAX

Strong scripting skills in Tcl & Python

Familiarity with Verilog/SystemVerilog and simulation environments

Excellent debugging and problem-solving skills

Good communication and excellent collaboration skills.