Build AI-powered freight operations tools by combining customer discovery with full-stack development, taking early prototypes into production and shaping the product’s technical direction.
Layout Scale-Up Engineer
📜 Description
- Build and own the PDK, including layer stack and technology files.
- Design a tile-based, hierarchical layout methodology for multi-chip designs.
- Write and maintain layout generators to automate GDSII/OASIS creation.
- Own the end-to-end mask generation process from floorplan to tape-out.
- Drive automation targets for layout efficiency at increasing qubit counts.
- Evaluate and deploy the EDA toolchain and integrate with EM-simulation.
🛠️ Requirements
- 5+ years in physical design, custom/analog layout, PDK development, or mask data prep in a semiconductor context (CMOS backend, RF/analog, MEMS, or photonics), including at least one production tape-out owned end-to-end
- Track record scaling a layout methodology — replacing hand-drawn layout with generators, PCells, or hierarchical flows on a design that grew substantially in element count
- Hands-on parasitic extraction experience — commercial (Calibre xRC/xACT, Quantus, StarRC) and/or field-solver-based (FastCap/FastHenry, BEM/FEM) — including deck/rule-file development and correlation against EM or measurement
- Strong layout-automation scripting: Python (gdstk/gdsfactory/KLayout API) and/or vendor languages (SKILL, Tcl)
- Fluent in DRC/LVS deck authoring, GDSII/OASIS, reticle and stepper constraints (field size, stitching, alignment marks), and tape-out data prep
- Comfortable turning a frequency plan or floorplan constraint set into geometry
- Fluent English and excellent written and verbal communication skills
✨ Benefits
- Our success is your success: own it with our BSPCE plan
- Direct IP Compensation: Earn substantial bonuses for driving the core patents that define our quantum architecture.
- Flexible remote policy, up to 40 % a month
- A Parental plan including additional benefits such as crèche support or additional days-off to take care of under 12 years old children
- Subsidized membership with Urban Sports Club
- Mental health support with moka.care
- 25-day vacation policy (as per French law) + RTT
- Half of transportation cost coverage (as per French law), or yearly allowance for the die-hard bicycle users
Full job description
About the Mission
About the Role
You'll build the layout infrastructure that makes that scaling possible — PDK, layout compilers, parasitic extraction, hierarchical verification, and mask generation. This is a semiconductor physical-design role applied to superconducting hardware, not a quantum physics one.
Responsibilities
Requirements
Nice to Have
Recruitment Process
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