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Experienced Formal Verification Engineer

📅 Mar 25, 2024
Formal VerificationDigital DesignComputer ArchitectureSystem-verilog
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📜 Description

  • Be the owner of formal verification environment from first draft to sign-off stage.
  • Apply formal methods to verify the correctness of various complex digital systems.
  • Work with HW architects/designers to define assumptions, rules and cover properties.
  • Help define the formal verification methodology and environment to be applied by the team.
  • Explore new formal methods and tools.
  • Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues.

🛠️ Requirements

  • BSc in electrical engineering, computer engineering, or computer science.
  • 5+ years of experience in Formal Verification.
  • Experience coding in system-verilog hardware description language.
  • Experience with scripting languages (e.g. python, tcl).
  • Strong analytical and problem-solving skills.
  • Ability to work independently and in a team-oriented environment.
Full job description

The Mobileye Automated Driving Hardware group in Haifa is looking for an Experienced Formal Verification Engineer to join a team of talented engineers developing next-generation silicon for autonomous driving platforms.

This is a unique opportunity to enter one of the most challenging and rewarding disciplines in hardware development. Formal Verification combines deep understanding of computer architecture, digital design, and advanced verification methodologies to prove hardware correctness and uncover bugs that traditional testing may never find.

Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

What will your job look like:

  • Be the owner of formal verification environment from first draft to sign-off stage.
  • Apply formal methods to verify the correctness of various complex digital systems.
  • Work with HW architects\designers to define assumptions, rules and cover properties.
  • Help define the formal verification methodology and environment to be applied by the team.
  • Explore new Formal methods and Tools.
  • Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago.
  • Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues.
  • Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf.
  • All you need is:

  • BSc in electrical engineering, computer engineering, or computer science.
  • Passion for the field of Formal Verification.
  • 5+ years of experience in Formal Verification.
  • Experience coding system-verilog hardware description language.
  • Experience with scripting languages (e.g. python, tcl ).
  • Strong analytical and problem solving skills.
  • Ability to work independently and in a team-oriented environment.
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