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2027 Internship - Formal Verification Engineer

🕒 3 days ago
Formal VerificationSystemverilogPythonPerl
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📜 Description

  • Support and improve formal verification methodology practices.
  • Develop test plans and verification methodologies for microarchitecture and design.
  • Analyze and resolve failures, and perform coverage analysis and population.
  • Implement and improve functional and formal verification.

🛠️ Requirements

  • Master’s or PhD degree in Electrical or Computer Engineering
  • Knowledge in designing and implementing verification environments for module-level designs.
  • Excellent communication skills and a collaborative approach to working with team members.
  • Proficiency in System Verilog.
  • Familiarity with scripting languages such as Python, Perl, TCL, Bash.
  • Experienced or knowledge in UVM or equivalent methodologies.
  • Knowledge in formal property languages such as SVA.
  • Knowledge in property-based model-checking.
  • Knowledgeable in signal processing, analog or digital design fundamentals.
Full job description
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!

Cirrus Logic is seeking an intern candidate for our Formal Verification team in Austin, TX. This position is focused on applying Formal Verification to digital designs. It is available to students currently enrolled in a MS or PhD program in Electrical and Computer Engineering. Candidate must be available for full-time employment during the internship.

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! Cirrus Logic follows a 2+ day in-office work schedule but interns should expect to be in the office more often, up to 5 days per week, based on business needs and team preference. Interns must be based within commutable distance of the work location listed on the job posting, or willing to relocate prior to beginning their internship with Cirrus Logic.   Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license.  Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role.   Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.

Responsibilities

  • Support the formal verification team to follow, and improve, defined methodology practices.
  • Develop test plans and verification methodologies to formally verify the microarchitecture and design.
  • Perform failure analysis and resolution, coverage analysis, and population.
  • Implement and improve functional and formal verification.
  • Required Skills and Qualifications:

  • Master’s or PhD degree in Electrical or Computer Engineering
  • Knowledge in designing and implementing verification environments for module-level designs.
  • Excellent communication skills and a collaborative approach to working with team members.
  • Proficiency in System Verilog.
  • Familiarity with scripting languages such as Python, Perl, TCL, Bash.
  • Experienced or knowledge in UVM or equivalent methodologies.
  • Knowledge in formal property languages such as SVA.
  • Knowledge in property-based model-checking.
  • Knowledgeable in signal processing, analog or digital design fundamentals.
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